1. Field Of The Invention
This invention relates to a non-volatile memory device, more particularly to a non-volatile memory device and an apparatus for reading a non-volatile memory array of the non-volatile memory device.
2. Description Of The Related Art
Mask Read Only Memory (MROM) is a popular non-volatile memory device in circuit design. Data is written into the memory cells of the memory device through a mask in the memory manufacturing process after the data is encoded. The data that is written into the memory cells of the memory device cannot be erased for rewriting of the memory device after the manufacturing process has been completed. Generally, MROM is used in storing large amounts of data, such as in television game programs and electronic dictionaries. Therefore, there is a need to increase the storage density of a memory cell.
Referring to FIG. 1, a conventional non-volatile memory device includes a non-volatile memory array (A1). The memory array (A1) includes a plurality of memory cells (C1) which are connected in parallel. Each of the memory cells (C1) has one bit of data stored therein and is formed from one of two different transistors. A voltage providing means (VP1) includes four NOR gates (G11 to G14) and two inverters (G9 and G10). Each of the NOR gates (G11 to G14) has an output terminal connected electrically to the gate of a respective one of the memory cells (C1). The first input terminals of two of the NOR gates (G11 and G12) are connected electrically to a first address line (A1), while the first input terminals of another two of the NOR gates (G13 and G14) are connected electrically to the first address line (A1) via the inverter (G10). The second input terminals of two of the NOR gates (G11 and G13) are connected electrically to a second address line (A0), while the second input terminals of another two of the NOR gates (G12 and G14) are connected electrically to the second address line (A0) via the inverter (G9). To read a memory cell (C1), the memory cell (C1) is addressed. At this time, the addressed memory cell (C1) is turned on, while the non-addressed memory cells (C1) are turned off. The drains of all of the memory cells (C1) are connected electrically to a sensing means (S1) for sensing whether the addressed memory cell (C1) is in a conducting state, that is, whether the addressed memory cell (C1) has current flowing therethrough after a gate voltage has been provided thereto. The sensing means (S1) consists of two inverters (G15 and G16) connected in series, and has an input terminal connected electrically to the drains of the memory cells (C1) and an output terminal connected electrically to a bit line (BIT) for the transmission of the data bit read from the addressed memory cell (C1). The sources of all of the memory cells (C1) are grounded. Some of the memory cells (C1) have a first threshold voltage, such as 0.7 v, that corresponds to data bit 0. The other memory cells (C1) have a second threshold voltage, such as 5.2 v, that is greater than the first threshold voltage and that corresponds to data bit 1.
Referring now to FIGS. 1 and 2, in operation, the voltage providing means (VP1) is configured to provide a test voltage between the first and second threshold voltages, such as 3 v, to the addressed memory cell (C1). The sensing means (S1) senses whether the addressed memory cell (C1) is in the conducting state after the test voltage has been applied thereto so as to determine the corresponding data bit.
Referring to FIG. 3, a second conventional non-volatile memory device includes a second memory array (A2). Unlike the memory array (A1) of FIG. 1, the memory cells (C2) of the memory array (A2) of FIG. 2 are connected in series. The voltage providing means (VP2) includes four NAND gates (G3 to G6) and two inverters (G1 and G2). Each of the NAND gates (G3 to G6) has an output terminal connected electrically to the gate of a respective one of the memory cells (C2). The first input terminals of two of the NAND gates (G3 and G4) are connected electrically to the first address line (A1) via the inverter (G2), while the first input terminals of another two of the NAND gates (G5 and G6) are connected electrically to the first address line (A1). The second input terminals of two of the NAND gates (G3 and G5) are connected electrically to the second address line (A0) via the inverter (G1), while the second input terminals of another two of the NAND gates (G4 and G6) are connected electrically to the second address line (A0). As with the previous example, to read a memory cell (C2), the memory cell (C2) is addressed. The addressed memory cell (C2) is turned off, while the non-addressed memory cells (C2) are turned on. Some of the memory cells (C2) have a first threshold voltage, such as -2.0 v, that corresponds to data bit 0. The other memory cells (C2) have a second threshold voltage, such as 0.7 v, that is greater than the first threshold voltage and that corresponds to data bit 1.
Referring now to FIGS. 3 and 4, in operation, the voltage providing means (VP2) is configured to provide a test voltage between the first and second threshold voltages, such as 0 v, to the addressed memory cell (C2). The sensing means (S2) senses whether the addressed memory cell (C2) is in the conducting state after the test voltage has been applied thereto so as to determine the corresponding data bit.
Referring to FIG. 5, in order to increase the storage density of a memory cell, a third conventional non-volatile memory device has been developed. The structures of the memory array (A3) and voltage providing means (VP3) of FIG. 3 are similar to those of the memory array (A1) and the voltage providing means (VP1) of FIG. 1. However, each of the memory cells (C3) stores two-bits of data therein and is formed from one of first, second, third and fourth transistors. The first transistor has a first threshold voltage, such as 0.7 v, and corresponds to data bits 00. The second transistor has a second threshold voltage, such as 2.2 v, greater than the first threshold voltage and corresponds to data bits 01. The third transistor has a third threshold voltage, such as 3.7 v, greater than the second threshold voltage and corresponds to data bits 10. The fourth transistor has a fourth threshold voltage, such as 5.2 v, greater than the third threshold voltage and corresponds to data bits 11.
The sensing means (S3) includes first to sixth inverters (G29 to G34) and first to sixth NAND gates (G35 to G40). The first and second inverters (G29 and G30) are connected in series. The third and fourth inverters (G31 and G32) are connected in series. The fifth and sixth inverters (G33 and G34) are connected in series. The input terminals of the first, third and fifth inverters (G29, G31 and G33) are connected electrically to the drains of the memory cells (C3). The first, second and third input terminals of the first and fourth NAND gates (G35 and G38) are connected electrically to the output terminals of the second, fourth and sixth inverters (G30, G32 and G34), respectively. The first input terminals of the second and fifth NAND gates (G36 and G39) are connected electrically to the output terminal of the first inverter (G29). The second input terminal of the second NAND gate (G36) is connected electrically to the output terminal of the fourth inverter (G32). The second input terminal of the fifth NAND gate (G39) is connected electrically to the output terminal of the third inverter (G31). The third input terminals of the second and fifth NAND gates (G36 and G39) are connected electrically to the output terminal of the sixth inverter (G34). The first and second input terminals of the third NAND gate (G37) are connected electrically and respectively to the output terminals of the first and second NAND gates (G35 and G36), while the first and second input terminals of the sixth NAND gate (G40) are connected electrically and respectively to the output terminals of the fourth and fifth NAND gates (G38 and G39). The output terminal of the sixth NAND gate (G40) is connected electrically to a first bit line (BIT1) for the transmission of a first one of the data bits of the addressed one of the memory cells (C3), while the output terminal of the third NAND gate (G37) is connected electrically to a second bit line (BIT2) for the transmission of a second one of the data bits of the addressed one of the memory cells (C3).
It should be noted that, the first inverter (G29) has a first trigger voltage, the third inverter (G31) has a second trigger voltage greater than the first trigger voltage of the first inverter (G29), and the fifth inverter (G33) has a third trigger voltage greater than the second trigger voltage of the third inverter (G31). Therefore, when the voltage level of the input signal presented at the input terminals of the first, third and fifth inverters (G29, G31 and G33) is located between the first and second trigger voltages, the first inverter (G29) has a low state output, while the third and fifth inverters (G31 and G33) have high state outputs.
Referring now to FIGS. 5 and 6, in operation, the voltage providing means (VP3) provides a test voltage between the third and fourth threshold voltages, such as 4.5 v, to the addressed one of the memory cells (C3). The sensing means (S3) senses whether the addressed one of the memory cells (C3) is in the conducting state after the test voltage has been applied thereto, and detects the value of the current flowing therethrough. If the current value is within a first predetermined range, the data bit 00 corresponding to the addressed one of the memory cells (C3) is detected. If the current value is within a second predetermined range small than the first predetermined range, the data bit 10 corresponding to the addressed one of the memory cells (C3) is detected. If the current value is within a third predetermined range between the first and second predetermined ranges, the data bit 01 corresponding to the addressed one of the memory cells (C3) is detected. If no current flows through the addressed one of the memory cells (C3), the data bit 11 corresponding to the addressed one of the memory cells (C3) is detected.
Since the sensing means (S3) of FIG. 3 must be capable of detecting the value of the current flowing through the memory cells (C3), the structure thereof is more complicated than that of the sensing means (S1,S2) of FIGS. 1 and 2, thereby resulting in a higher manufacturing cost.
Referring to FIGS. 7 and 8, a fourth memory array (A4) is shown. However, the value of the current flowing through the addressed one of the memory cells (C4) is indeterminated since the memory cells (C4) are connected in series. Therefore, the memory array (A4) of FIG. 7 is unusable because the sensing means (S4) cannot be defined.